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uOttawa Description: Description: arrowEngineering Description: Description: arrowSITE Description: Description: arrowStaff Description: Description: arrowMiodrag Bolic

 

CEG4136 Computer Architecture III                

 

Instructor: Dr. Miodrag Bolic 
 

News

Catalog Description

Instructor and Teaching assistants

Time and Locations

Required Texts

Additional documents

Prerequisites

Grades

Course Outline

Laboratory

Assignments

 

Last change: August 29, 2013

NEWS                                                                                                                         

 

CATALOG DESCRIPTION                                                                                                                                   

Multiprocessor systems: vector processors, array processors, SIMD, MIMD systems. Interconnection networks. Multiprocessor architecture and programming. Multiprocessing control and algorithms. The PRAM model and algorithms. Message-passing models and algorithms. Scheduling and arbitration algorithms. Parallel virtual machine. Message passing interface. Performance measures for multiprocessor systems.

 

 

INSTRUCTOR AND TEACHING ASSISTANTS                                                                                             

 

Course staff

Name

E-mail address

Fall 2011 Office Hours

Location

Instructor

Miodrag Bolic

mbolic@site.uottawa.ca

Wednesdays, 12:00-13:00,

 

CBY A-616

Teaching assistants

By e-mail

 

 

 

 

TIME and LOCATIONS                                                                                                                            

 

Activity

Time

Location

Room

 LEC

 Monday, 10:00-11:30

 LMX              

 Room: 342

 LEC

 Wednesday, 08:30-10:00

LMX

 Room: 342

LAB

Friday 14:30-17:30

SITE

 

TUT

Monday 14:30 – 16:00

SITE

F0126

 

 

 TEXTS                                                                                                                                                         

 

Parallel Computer Organization and Design, by Michel Dubois, Murali Annavaram, Per Stenström, August 2012

 

 

Recommended:

Advanced Computer Architecture and Parallel Processing, by Hesham El-Rewini and Mostafa Abd-El-Barr, John Wiley and Sons, 2005.

http://ca.wiley.com/WileyCDA/WileyTitle/productCd-0471467405.html

 

Advanced Computer Architecture Parallelism, Scalability, Programmability, by  K. Hwang, McGraw-Hill 1993.    

 

Computer Architecture: A Quantitative Approach, by John L. Hennessy, David A. Patterson, David Goldberg, Morgan Kaufmann; 3rd edition, 2002.

 

Multiprocessor Systems-on-Chips (The Systems on Silicon Series) by Wayne Wolf, Morgan Kaufmann, 2004.

 

Advanced Computer Architectures – A Design Space Approach by Desco Sima, Terence Fountain and Peter Kascuk, Pearson, 1997.

 

 ADDITIONAL DOCUMENTS                                                                                                                                                    

 

Appendix E from Computer Architecture: A Quantitative Approach together with the slides.

 

 

PREREQUISITES                                                                                                                                      

:

CEG3131.

 

GRADES                                                                                                                                                                              

 

30% Particitation and Short Questions

40% Final

30% Labs

The final mark will be computed using the weighted sum of ALL of the above components. You need to have 50% of the exam component that includes Final and “Participation and Short Questions”

There will be quizzes every week. You will be required to prepare for the class and to read in advance. The quiz will include questions covered during last week and topics that you read in preparing for the class.

 

 

EXAMS (FINAL)

·         All exams are closed book.

·         Only material cover in the class, tutorials and labs will be on the exam.

 

QUESTIONS ABOUT MARKS

If you have a question about a mark you have received, this is the procedure (all other questions on marks will be ignored)

·         Schedule an appointment with the T.A. to see the work (if required).

·         Fill out and sign form (obtained from T.A., or download it herethanks to dr. Andy Adler for developing the form)

·         Submit to T.A.

·         You will receive a response within two weeks.

GRADING

Name

Quiz

Lab

Project or literature study

Exams

Miodrag Bolic

-

-

-

Final

Iype Joseph

All quizzes

Labs

-

-

 

 

 

 

 

COURSE OUTLINE                                                                                                                                              

 

Introduction: Chapter 1

Cache memories: Chapter 4.3

 

Parallel-programming model abstractions and message passing MP systems: Chapter 5.2 and 5.3

Bus-based shared memory systems: Chapter 5.4

Scalable and cache only memory systems: Chapters 5.5 and 5.6

 

Interconnection networks: design space, switching and topologies: Chapters 6.2, 6.3 and 6.4

Routing and switching architectures: Chapters 6.5 and 6.6

 

Background and coherence: 7.2 and 7.3

Consistency: 7.4

Synchronization: 7.5

Relaxed memory model and speculative violation of memory orders: 7.6 and 7.7

 

Multithreading: 8.2 and 8.3

Chip processor architectures and programming models: 8.4 and 8.5

 

LABORATORY

 

 

SLIDES AND MADETIAL FROM 2012                                                                                     

 

Note: Lecture slides will in general be available for download before the lecture.

Lecture scribing from 2006 (Disclaimer: please note that all the material is written by students and did not go through peer review process. Be careful and critical when reading this document. Please send me your comments if you see typos or some problems with the material).

 

Topic number

Topic

Scribing from 2006

Literature

T1.    

Introduction, Review of cache memories

Lecture 1,2

 

T2.    

Performance analysis

Lecture 3

 

T3.    

Parallel models

Lecture 4

 

T4.    

Buses

Lecture 5

 

T5.    

Dynamic interconnection networks

Lecture 6,7

 

T6.    

Static networks

Lecture 8

 

T8.    

Shared memory systems

Lecture 9

 

T9.    

Cache coherence

Lecture 10,11

 

T10

GPU architectures: Slides, Doc, OpenCL: Slides, Doc

Lecture 12,13

 

T11

OpenMP, OpenAcc

 

 

Lecture 14

OpenMP Presentations:

·         OpenMP: An API for Writing Portable SMP Application Software: pdf (Slides 9-13, 17-19, 21-27)

http://www.openmp.org/presentations/sc99/sc99_tutorial.pdf

·         ICC’s High Performance Computing: OpenMP

http://www.llnl.gov/computing/tutorials/openMP/

 

OpenAcc 

http://www.ccs.tsukuba.ac.jp/CCS/files/slides/1205_LuizDeRose.pdf

T11.                         

Routing 1, 2

Lecture 15

 

T13.                         

Deadlock

Lecture 16

 

T14.                         

Message passing systems, MPI programming

Lecture 17

 

T15.                         

Embedded multicores

 

 Freescale Semiconductor, EmbeddedMulticore: An Introduction, , EMBMCRM, Rev. 0, 07/2009

T16.    

Network on chip

Lecture 18

 

T17.                         

Cache coherence for multicore computers

 

Chapter 2: On-Chip Networks 

Natalie Enright JergerLi-Shiuan Peh

2009

Abstract | PDF (2472 KB)

        T18.   

 Router microarchitecture

 

 Chapter 6: On-Chip Networks 

Natalie Enright JergerLi-Shiuan Peh

2009

Abstract | PDF (2472 KB)

 T19.          

 Cloud computing

 

 Introduction to Cloud Computing, Jonathan Parri, Report, University of Ottawa, 2011.

T20.

Review

 

 

 

 

 

 

ASSIGNMENTS FROM 2004 and QUIZES FROM 2005-2007                                                                                                                                    

There will be assignments from textbooks which will not be collected. Some assignments might include working with simulators.

 

Assignment

Problems

Solutions

1

Assignment 1

Assignment 1 Solutions

2

Assignment 2

Assignment 2 Solutions

3

Assignment 3

Assignment 3 Solutions

4

Assignment 4

Assignment 4 Solutions

5

Assignment 5

Assignment 5 Solutions

 

 

 

 

Quizzes from 2007

Quiz 1 Solutions

Quiz 2 Solutions

 

 

Quizzes from 2006

Quiz 1 Quiz 1 Solutions

Quiz 2 Quiz 2 Solutions

Quiz 3 Quiz 3 Solutions

Quiz 4 Quiz 4 Solutions

 

 

Quizzes from 2005

Quiz 1 (Chapters 1,3)  Quiz 1 Solutions

Quiz 2 (Chapters 2)  Quiz 2 Solutions

Quiz 3 (Chapter 5)   Quiz 3 Solutions

Quiz 4 (Additional literature)   Quiz 4 Solutions

Midterm solutions

Final

Final