Digital Design I

Summer 2014

Aziz Abdesselam

Email: abdessel@site.uottawa.ca, Office: CBY A505

(01/05/2014-23/08/2014)

1. Syllabus

2. Lecture Notes (From prof. Karmouch)

• Chapter 1: Binary Systems (ch1.pdf)

• Chapter 2: Boolean Algebra and Logic Gates (ch2.pdf)

• Chapter 3: Gate - level Minimization (ch3.pdf)

• Chapter 4: Combinational Logic (ch4.pdf)

• Chapter 5: Synchronous Sequential Logic (ch5.pdf)

• Chapter 6: Registers & Counters (ch6.pdf)

3. Homeworks

   • HW1 (Due the 23/05/2014 to the TA during the lab session) solution

     HW2 (Due the 06/06/2014 to the TA during the lab session) solution

   • HW3 (Due the 04/07/2014 to the TA during the lab session) solution

   • HW4 (Due the 018/07/2014 in the course mailbox before 1pm) solution

4. Laboratories

   • Documentation: Lab. Manual,

   • ALTERA MAX Pin Connectors,

   • Lab0: Tutorial on upcoming lab work and tools. To be done Friday May 9th, 2014. no report due

   • Lab1: Logic gates. To be done Friday 16th, 2014. Lab. reports due May 23rd to the TA in the lab.

   • Lab2: Boolean Logic. To be done Friday May 23rd, 2014. Lab. reports due May 30th to the TA in the lab.

   • Lab3: Decoders, Displays and Multiplexers. To be done Friday May 30th, 2014. Lab. reports due June 6th to the TA in the lab.

   • Lab4: Arithmetic Circuits To be done Friday June 6th and 13th, 2014. Lab. reports due June 20th to the TA in the lab.

   • Lab5: Latches and FLip FLops. To be done Friday June 20th and 27th, 2014. Lab. reports dJuly 4th to the TA in the lab.

   • Lab6: Synchronous Counters. To be done Friday July 4th and 11th, 2014. Lab. reports due July 18th

5. Midterm (June 16th STE A0150) Grades

6. Final (July 26th at 1pm in STE G0103)